In January 2010 the layout of the UniBoard was completed and manufacture itself could begin. A correlator design document was written and reviewed. VHDL design and simulations continued at all institutes and most test firmware, which in many cases will be used as application building blocks, has been completed. SHAO officially became a partner when the RadioNet FP7 contract was formally amended. The board itself continues to generate considerable interest in the radio-astronomical community, and several groups are considering using the board as a LOFAR all-station correlator. In this context Oxford University, already member of RadioNet FP7, decided to join the UniBoard project as well, bringing the total number of partners to nine. The first prototype will be delivered right on time, and the project as a whole remains on schedule.

Documents:

• Draft UniBoard EVN correlator design, Jonathan Hargreaves and Harro Verkouter, 13-01-2010
• UniBoard hardware design, Gijs Schoonderbeek and Sjouke Zwier, 29-01-2010
• UniBoard Schematic, Gijs Schoonderbeek and Sjouke Zwier, 29-01-2010
• RFI Mitigation Implementation for Pulsar radio astronomy, D.Ait-Allal et al., paper submitted to EUSIPCO 2010 conference, August 2010.

General activities in Q5:

• 2-weekly project-wide general telecons
• monthly JIVE/ASTRON Correlator Implementation and Control meetings
• 2-weekly ASTRON/JIVE internal technical meetings

Activities by institute in Q5:

ASTRON:

• board layout finished; now in production
• several iterations with production company to optimize the manufacturability
• document written on re-usable firmware (not yet on wiki)
• implementation of re-usable FFT module
• initial design of adapter board (XGB, 10G Break-out board)
• interface and protocol between control computer and board defined and refined, partly implemented
• design and simulations for interface between front and back node FPGAs
• completed firmware: simple LED example to prove functionality of JTAG interface, DDR memory interface, FPGA mesh, NIOS design and SPI chip read/write
• document produced describing test suite
• correlator design document review

BORD:

• mathematical model of digital filter refined
• statistics module (signal distribution, power etc.) has been validated
• the various modules have been linked to the NIOS
• VHDL design of the different modules of the front node FPGA (polyphase filer + 16-points FFT + configurations & communications modules) was completed
• design of the fast ADC is complete at the schematic level (3-bit design in a first step); testing of associated T/H ASIC was successfully completed on a test PCB

INAF

• the preliminary design for the front and back node FPGAs has been integrated in a SOPC (System on Programmable Chip) processor, using the general SOPC architecture developed for the board
• second stage of the FFT polyphase filter and the variable decimation tunable filter, in the second stage chip, have been coded and tested

JIVE:

• detailed schematic review in January. Several minor problems found and corrected
• transceiver power supply configuration changed to accomodate an Altera data sheet change
• progress with test designs: designs to test DDR, configuration memory, I2C, INTA/B and watchdog reset completed and verified. Designs to test the 10G ports and the front-back node mesh are in progress: will also serve as infrastructure blocks in applications such as the EVN correlator
• draft design EVN correlator placed on wiki in January
• detailed design of correlator control software in progress, revised document to be ready in Q6
• work on Erlang VEX parser
• mapping of VEX file to SQL database scheme
• first version of de-channelizer completed, which decodes multi-channel MarkIV data and recodes it into single-channel VDIF; decoding available in Erlang and in just-in-time compiled
• single- and/or multiple bit data with various fan-out modes successfully tested on software correlator
• C-code base for hardware agnostic parts of embedded NIOS CPU in place
• client Erlang code for FPGA control written; verified agains emulators written in Erlang (direct connection) and C (via UDP/IP)
• work started on Erlang GUI for test applications

KASI:

• work has not started in Q5

UMAN:

• work on 10G ethernet routing and use
• Matlab simulation package of pulsar dispersion & dedispersion completed
• report written on first simulations and dedispersion tests

UORL:

• tests on real data with Matlab
• study of a new pulsar search method (giant pulse oriented for the moment)

SHAO:

• work has not started in Q5

Problems / Issues

• crosstalk and influence between high-speed traces are still not clear, in next quarter this will be investigated further

Issues - organizational, administrative or other problems foreseen

• JIVE needs to hire a new firmware engineer soon
• BORD contract for Pascal Camino will expire in Q6. A face-to-face meeting in Bordeaux with INAF is planned in April 2010 to discuss available manpower and task takeover

Red flags - major problems

• none

Forward Look (till end of 2010)

ASTRON:

• PCB assembly in Q6
• first prototype in Q6
• all required test firmware will be done in Q6
• 8-board production run (Q7)

BORD:

• meeting in Bordeaux on fully integrated digital receiver design and UniBoard applications
• work on digital receiver documentation
• assist with UniBoard debugging
• host UniBoard face-to-face meeting in Bordeaux (Oct. 2010)
• continue fast ADC design including de-multiplexing stage; at foundry Nov. 2010

INAF:

• completion of HDL coding of both FPGA cores
• integration of cores in common SOPC UniBoard structure

JIVE:

• finish test design mid April 2010
• test board and revise design May-July 2010
• correlator firmware development April-August 2010 (“proof of concept” correlator to test autocorrelations and correlate delay-corrected data)

KASI:

• one KASI engineer will visit JIVE/ASTRON in Q5/Q6, to assist in hardware tests

UMAN:

• complete analysis of real baseband data (20MHz) from the WSRT to test Matlab code
• expand simulations to include wider bandwidths, polyphase filters etc.
• continued development of data distribution models/plans for UniBoard
• migrate simulations from floating point to fixed point for implementation on FPGA
• start development work on other pipelines, eg searching, incoherent dedispersion
• migrate from a model based simulation to an FPGA targeted design and simulation

UORL:

• meetings with UMAN, before and after summer 2010
• Matlab simulation on real data from Nancay telescope; continuous update of the RFI mitigation algorithm architecture in collaboration with UMAN
• Matlab model of this architecture (Sep. 2010)
• test of gold model on synthetic and real data
• engineering position will become available June 2010
• start of VHDL coding

SHAO:

• 2 digital engineers may visit Dwingeloo towards the end of Q6; no formal decision has been taken yet

Expected milestones/ deliverables

• hard and firmware design documents, month 11:
  • hardware and digital receiver design documents were completed in months 9 and 10, correlator design document was completed in month 13, due to the late start of work at UMAN the pulsar binning machine design document was delayed but should be completed before the end of Q6.

• first generation board, month 17:
  • currently first prototype board is expected in month 17

• Expenditures - equipment, material and services:
  • the complete UniBoard hardware budget was spent in year 1 on 64 Altera FPGAs, various components and PCB manufacture. Because the manufacture has not been paid yet, this does not appear in the budget. Extra materials were ordered for the SHAO board, these are paid through an MoU