During this period a great deal of activity took place in the UniBoard project. Testing of the prototype was completed and with it a revised hardware design. A production run got underway at the end of 2010, with expected delivery of 8 boards in April - May 2011. XGB boards and enclosures were produced and delivered. Thanks to the re-division of funds within RadioNet it became possible to populate all boards with 4 GB DDR3 memory modules. Revised hard- and firmware design documents were written, fulfilling all deliverables (due by month 27) just a few days after the end of Q9. A very successful and well-attended face-to-face general project meeting was held in Bordeaux in October 2010. Finally, an Erlang high level programming/UniBoard control code tutorial was held at JIVE, featuring live streaming video through EVO, enabling participants from outside the Netherlands (and some within the Netherlands but outside the building) to participate interactively.

Documents

• Removing FN2 UniBoard Sjouke Zwier, 11-10-2010
• UniBoard Interconnection PCB production meeting Gijs Schoonderbeek, 20-10-2010
• UniBoard rev. 2.0 Schematic Gijs Schoonderbeek, Sjouke Zwier, 17-11-2010
• UniBoard rev. 2.0 Board Description Gijs Schoonderbeek, Sjouke Zwier, 04-11-2010
• Uniboard firmware development. Eric Kooistra, 04-11-2010
• XGB rev. 2.0 Schematic Gijs Schoonderbeek, Sjouke Zwier, 09-11-2010
• Testing 10 Gigabit links between UniBoard and a PC. Jonathan Hargreaves, 15-11-2010
• X-ray images of UniBoard, Neways/Fix Trade, + TDR Measurements + PCB cross sections Astron design team, 26-11-2010
• UniBoard power estimation Gijs Schoonderbeek, 17-12-2010
• UNIBOARD Pulsar Project Definition, PDS-020:0.1 Aziz AhmedSaid, Chris Shenton, Rob Ferdman, Ben Stappers, 14-03-2011
• Uniboard transceiver firmware module. Daniel van der Schuur, 10-03-2011
• Uniboard SVN draft database structure, see SVN General/ for latest revision. Eric Kooistra, 17-01-2011
• 1Gb Ethernet Module description. Eric Kooistra, 02-02-2011
• UNB_Common Module Description. Eric Kooistra, 03-02-2011
• Specification for module interfaces using VHDL records and wrappers. Eric Kooistra, 03-02-2011
• A UniBoard-based Phase 1 SKA Correlator and Beamformer Arpad Szomoru et al., 04-02-2011
• UniBoard 2: Delivery package and recommendated peripherals Gijs Schoonderbeek, 18-03-2011

not quite within reporting period:

• EVN Correlator Design revised March 2011. Jonathan Hargreaves, Harro Verkouter, 01-04-2011
• UniBoard digital receiver revised design doc Gianni Comoretto, et al., 05-04-2011

General activities in Q8 - Q9:

• 4-weekly project-wide general telecons
• monthly JIVE/ASTRON Correlator Implementation and Control meetings
• 2-weekly ASTRON/JIVE internal technical meetings
• 2-weekly internal technical meetings at UMAN
• UMAN-UORL meetings (December 2010, February 2011)
• face-to-face general meeting, Bordeaux, October 12-13, 2010
• Erlang tutorial, Dwingeloo, February 11 2011
• Visit by Shenton to JIVE/ASTRON, February 2011

Activities by institute in Q8 - Q9:

ASTRON:

• Finalizing of hardware design, sent out for production
• Memory modules ordered and received
• (with JIVE) Control infrastructure fixed, software issue in switch device solved
• XGB board tests
• 8 XGB boards are produced and ready
• Design of metal enclosure including fans
• 8 enclosures currently ready for boards
• (with JIVE) Integrated test firmware with following modules: SPI flash access, PPS, I2C sensors, DDR3 access, transceivers FN-BN mesh, transceivers via XGB between BN nodes, 10 Gb Ethernet between FN nodes, 1 Gb Ethernet implicit via test control

BORD:

• Review of documentation
• Building up experience with Erlang
• Dommunication test between Erlang server and Python client using UDP

• In parallel with the DBBC work, the full design of a 8GS/s, 3-bit ADC (CMOS 65 nano) was finalized and sent to the foundry in January 2011
• Designing of 6-bit functional blocks continues

INAF:

• Simulation of whole design, excluding 10G IP interface
• Design of a test signal generator
• Documentation

JIVE:

Test Design:

• (with ASTRON) Complete test designs prepared for verifying the new boards

EVN Correlator Design:

• Several firmware modules have been coded, verified and are ready to integrate into the top level design: Correlator Engine, Polyphase Filter Bank (including multi-channel FFT), FN-BN Interface.
• Other firmware modules are coded and currently being verified: Delay Module, Input Buffer (including FN control logic).
• The last module, the Corner Turner, has not been coded but a design specification has been written for it.

Board control:

• Finalized embedded code that runs on the NiosII CPU on the FPGA, for comman processing and execution
• Finalized Erlang client code which interfaces between the user and the UniBoard's FPGAs, ultimately allowing the control of all FPGAs on a UniBoard from a single command.

KASI:

• Work has not started in Q8 - Q9

UMAN:

• Completion of description and analysis of how to perform the large FFTs required for coherent dedispersion
• Description of the message passing requirements of the pulsar processing modes
• Analysis of how the existing tools in the UniBoard repository might be reused for the pulsar processing modes and identifying which tools will need to be written in full.
• Iteration on the architecture of the proposed coherent dedispersion implementation and first steps towards modularization
• Analysis (and documentation) of the sizing and initial design of the pulsar search mode for the UniBoard
• Specification and acquisition of a test board (with FPGA similar to those used on UniBoard)

UORL:

• Study into the possibility of re-designing the digital receiver (DBBC) for 1 GHz (2 GS/s), which would fit on a single FPGA. The output will be 16 x 64MHz complex signals at 64 Msamples/s. Currently under discussion with BORD and INAF
• Implementation in VHDL of two RFI mitigations algorithms for one channel: the cyclostationary detector and the pulse power detector

In order to improve the quality of the astronomical observation, two RFI managing options are proposed:

• Generation of a flag indicating the presence of RFI, leading to a clean and a polluted data profile at the end of the folding process. In this way no lossed occur and posteriori checks remain a possibilty
• Replacement of polluted samples by fake but “clean” samples. Comparison, in the case of coherent pulsar dedispersion, of four fake samples generations:

1. zeroes
2. chosen randomly from clean observed signal
3. chosen in order from clean observed signal
4. regenerated according to signal distribution

leads to the conclusion that solution 2 provides the best results

UOXF:

• No input received

SHAO:

• A ModelSim license was obtained
• Development of 1K points pholyphase filter + parallel FFT core was completed on Xylinx-based Chinese dBBC board; this code will be ported to the UniBoard
• Design of a 5Gsps ADC board with a commercial chip and 10GE interfaces has been started, which will be connected to the UniBoard

Problems/issues

• The problem using the CMU transceiver channels has not been resolved, so it is still only possible to use 12 external 10GE ports on each side of the UniBoard
• Not a problem but a risk: it was not possible to run the DDR3 tests at full speed due to problems with the DDR3 power supplies. The problems should be resolved on the new boards but we can't be sure until we receive them

Red flags - major problems

• none

Forward look

ASTRON:

• Delivery of all UniBoards
• Integration with XGB and enclosure
• UniBoard testing
• Integrated test firmware image available for all partners
• Completion of UniBoard firmware platform document to ship with the board

BORD:

• Q10: Continuation of work on Erlang / Python software to be able to control and monitor the DBBC design. Task sharing will be discussed with INAF

INAF:

Q10:

• Adaptation of the 10G UDP/IP formatter designed at JIVE/ASTRON
• Adaptation of the front node/back node interconnect mesh
• Documentation

Q11:

• Tests with actual board

JIVE:

Q10:

• EVN Correlator firmware integration to perform signal flow tests in both simulation and hardware.
• Finalization of documentation on board control
• Reorganization of Erlang codebase as a direct effect of attending “Erlang University” course on how to actually organize code and applications in Erlang.

Q11:

• EVN Correlator: Integration of delay module and test design with real data

Q12:

• EVN Correlator: Expansion of operating modes, increase of power efficiency

SHAO:

• In Q11 - Q12 two engineers from ShAO will visit Jive/Astron for an extended period, to gain familiarity with the UniBoard architecture and Altera development tools

UMAN:

Q10:

• Implementation of 2 x 10G UDP frame loopback test harness based on a STRATIX IV eval board, and standard Altera 10G IP
• Implementation of dummy DSP block and frame pass through loop test
• Integration of dedispersion block into test harness
• Implementation of UniBoard NIOS 2 based Control Plane processor and associated Erlang control code.
• Creation of an architecture for large FFTs
• Implementation of a dedispersion coefficients generator, polyphase filter bank, folding architecture, full dedispersion architecture

Q11:

• Transition of Eval Board based designs to UniBoard
• Implemention of a Taylor Tree architecture
• Assembly of full searching architecture
• Testing on actual board

UORL:

• Validation of the implementations with Matlab and Simulink
• Extension of the two RFI mitigation algorithms to several channels simultaneously
• Testing of the implemented RFI mitigation algorithms on Altera BeMicro SDK
• Testing of the implemented RFI mitigation algorithms on the actual board

Expected milestones/ deliverables

All deliverables are in place, the next and final deliverables are due in month 36. Milestone 9.5, conclusion system test, due in month 27, was in fact reached with the successful completion of the testing of the UniBoard prototype. The delivery of the production boards however, along with the completed firmware test suite, will be the real milestone. This is expected end of April, beginning of May 2011.